(1) Field of the Invention
This invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to form well regions for N channel, and for P channel, metal oxide semiconductor field effect transistors.
(2) Description of Prior Art
The advent of complimentary metal oxide semiconductor (CMOS), technology, featuring N channel (NFET), and P channel (PFET), devices, on the same semiconductor chip, created the need for twin wells, specifically an N well region to accommodate the PFET devices, and a P well region for the NFET devices. To satisfy density, as well as performance requirements, it is imperative that the twin well regions be self-aligned, minimizing the area needed for these regions, as well as minimizing the distance between the conductive structures used for communication between the different type devices. One method of satisfying the self-alignment requirement is the formation of a first well region, such as the N well region for the PFET or PMOS type devices, in a region of a semiconductor substrate exposed in an opening formed in an overlying silicon nitride layer. This is followed by an oxidation procedure which results in a thick silicon dioxide layer on the N well region, while silicon dioxide growth is retarded by the silicon nitride layer overlying a region of a lightly doped, P type semiconductor substrate, to be used to subsequently accommodate the P well region. After removal of the silicon nitride layer an ion implantation procedure is employed to place the P type ions, needed for formation of the P well region, into the portion of the semiconductor substrate not blocked by the thick silicon dioxide layer, located overlying the N well region, thus self-alignment of the twin wells is realized.
The present invention will describe a novel procedure for forming self-aligned, twin well regions, without the use of silicon nitride, thus reducing process costs, as well as avoiding the process complexity of depositing, patterning, and removing silicon nitride. This invention will feature the different oxidation rates of N type doped silicon, and lightly doped P type silicon, to achieve an non-silicon nitride procedure for formation of self-aligned twin wells. Prior art, such as Kim et al, in U.S. Pat. No. 5,766,970, as well as Schwabe et al, in U.S. Pat. No. 4,434,543, describe methods for obtaining self-aligned twin well regions, however these prior arts feature the use of a patterned, silicon nitride layer, to accomplish the self-aligned objective.
It is an object of this invention to form twin well regions, to accommodate CMOS designs comprised of PFET as well NFET devices.
It is another object of this invention to form the twin well regions for CMOS designs, employing procedures resulting in self-aligned twin well regions.
It is still another object of this invention to minimize fabrication cost, and reduce process complexity, via forming self-aligned twin well regions, without the use of a patterned silicon nitride layer, as an oxidation retarding mask.
In accordance with the present invention a method of forming self-aligned, twin well regions in a semiconductor substrate, via use of differential oxidation rates on specifically doped regions, without the use of a silicon nitride, oxidation retarding layer, is described. A photoresist shape is used as a mask to allow N type ions to be implanted into first region of the semiconductor substrate, exposed in an opening in the photoresist shape. A thermal oxidation procedure is then employed resulting a thick silicon dioxide formation, on the first region of the semiconductor substrate, with a N well region formed directly underlying the thick silicon dioxide layer. A thinner silicon dioxide layer is formed on second regions of the P type, semiconductor substrate. A second ion implantation procedure is performed to allow P type ions to be implanted through the thinner silicon dioxide layer, into second regions of the semiconductor substrate, while the thicker silicon dioxide layer prevents the P type implantation from entering the N well region. An anneal procedure is then used to activate the P type ions, resulting in P well regions located in second regions of the semiconductor substrate, self-aligned to the N well region, located in the first region of the semiconductor substrate.